Prior to hardware fabrication, one technique of examining and verifying a design of a hardware component, such as an integrated circuit, is to model the operation of the design in software and then perform verification testing on the model. For the purpose of modeling the design, the functionality may be described, for example, using a hardware design language (HDL) such as Verilog. HDL may represent various functions or operations of the hardware design as separate models or statements in the HDL code.
The software emulation of the hardware (referred to, hereinafter as “source code”) may be operated in different configurations to test or verify operation of various functionalities of the hardware component. A test may cause execution of all or some of the statements in the HDL code. A fraction or percentage of the statements or other entities in the HDL code that are covered by a test may be referred to as coverage. Coverage may relate to the entire set of HDL code, or to a part or block of the HDL code. Coverage may also refer to code (e.g., whether a block of code has been executed during a test), expressions (e.g., whether all possibilities in a truth table have been covered by a test), functionality, or other facets of the emulation.